1. Field of the Invention
The present invention relates to an analog-to-digital converter. More specifically, the present invention relates to a multi-stage dual successive approximation register analog-to-digital converter (SAR ADC), which implements one SAR ADC stage using two SAR ADCs for a high-speed analog-to-digital conversion, and a method of performing analog-to-digital conversion using the same.
2. Discussion of Related Art
Analog-to-digital converters (ADCs) convert continuous analog signals into discrete digital signals that represent the magnitude of the continuous signals. Examples of ADCs include a pipeline ADC, a successive approximation register (SAR) ADC, an algorithmic ADC, and so on.
The SAR ADC has a simple structure in which one comparator is repeatedly used. It is power and space-efficient and can be easily applied to low-power circuit, because it does not require an analog circuit using an amplifier such as a sample-and-hold amplifier (SHA). The SAR ADC, however, has a structure that repeatedly uses the same circuit, so that its operating speed is limited to about tens of MHz.
For this reason, most conventional high-speed, high-resolution ADCs have been implemented using a pipeline ADC.
FIG. 1 is a schematic view illustrating the structure of a conventional pipeline ADC.
Referring to FIG. 1, the conventional pipeline ADC includes an SHA 110 sampling/holding an original analog input voltage Vin, sub-ranging ADCs 120a and 120b, a flash ADC 130, and a digital correction circuit 140.
In this conventional pipeline ADC, the sub-ranging ADCs 120a and 120b sequentially perform digital conversion on the analog input voltage Vin, and the flash ADC 130 performs digital conversion on a last bit (a least significant bit (LSB)). Digital conversion resolution of the final analog input voltage Vin is equal to the sum of resolutions of the sub-ranging ADCs 120a and 120b and the flash ADC 130.
Here, each of the sub-ranging ADCs 120a and 120b includes a multiplying digital-to-analog converter (MDAC) block, which has an SHA 121, an adder 123, an amplifier 125, and a digital-to-analog converter (DAC) 127, and a flash ADC 129.
As for operation of the sub-ranging ADCs 120a or 120b, when an analog signal is input from a preceding stage, a part of the analog signal is converted into a digital signal by the flash ADC 129, and then the converted digital signal is again converted into an analog signal by the DAC 127.
Afterwards, the analog signal sampled by the SHA 121 and the analog signal converted again by the DAC 127 are added by the adder 123, and the added analog signal is amplified by the amplifier 125 and output to the following stage.
As such, the pipeline ADC includes the sub-ranging ADCs 120a and 120b, each of which converts a part of the input signal into digital. Thus, the pipeline ADC allows relatively fast digital-to-analog conversion with high resolution.
However, since the SHA 110 is located at the input stage, noise and nonlinear characteristics generated by the capacitor and amplifier affect the entire ADC, deteriorating its performance. Further, the number of comparators used by the flash ADC 129 increases by a power of two as required resolution increases. Thus, if a flash ADC with three or more bits is used, area greatly increases.